1. Field of Invention
This invention relates to a layout structure for providing a stable power source More particularly, this invention relates to a layout structure for providing stable power source to a main bridge chip substrate and a motherboard.
2. Description of Related Art
With fast developing technology, the operation speed of computers is getting faster and faster. Taking Intel Pentium 4 as an example, the CPU bus speed can reach 532 MHz (133 MHz×4). This means that the main bridge chip is required to provide higher bus speed on other buses to work with the peripheral components connected to it. The buses include the memory bus with the speed of 333 MHz (166 MHz×2), the AGP bus with the speed of 528 MHz (66 MHz×8) and the main-subalternate connecting bus with the speed of 66 MHz×8. In addition to the high operation speed in requirement, the layout of the main bridge chip substrate as well as the motherboard have to be well designed in order to achieve stable operations for the above devices. Normally, certain design sequences have to be followed during designing the layout of the main bridge chip and motherboard. For example, in order to stabilize a good signal quality on the signal layer, a ground layer has to be provided on the main bridge chip substrate or the motherboard, close to the signal layer, so that all the signals on the signal layer can be referenced to the ground layer.
However, the existing signal-referencing method mentioned above often has some problems depending on how the layout is designed for the main bridge chip substrate and the motherboard FIG. 1 shows a conventional circuit layout for the main bridge chip substrate and the motherboard, wherein there are 4 layers from top to bottom by the top signal layer 11, the ground layer 12, the power source layer 13, and the bottom solder layer 14 respectively. In the conventional layout for the motherboard and the main bridge chip substrate, almost all of the signals in layout are arranged the top signal layer 11, so that the signal lines can be referenced to the ground layer 12. On the other hand, various types of power sources can be obtained through the layout and partition on the power source layer 13. Moreover, the bottom solder layer 14 of the main bridge chip substrate normally contains the solder balls for soldering to the motherboard. Also and, the other circuits for which the signal quality is not critical can also be arranged into this bottom solder layer 14. However, when the main bridge chip needs an even higher bus speed (higher than 1 GHz for example), the layout of the main bridge chip substrate and the motherboard becomes very important because it consumes more power for the relating controllers and the interfaces The layout of the power source is then a rather more important issue.
FIG. 2 shows a schematic diagram of an existing layout structure of the main bridge chip on the power source layer 13 of the motherboard 200, where the partition of the power layer 13 is also indicated in FIG. 2. Furthermore, FIG. 2 also shows many bonding pads which are located at the top signal layer 11 and are connected with the power layer 13 through the vias. It should be noted that the bonding pads must be arranged and positioned according to the locations of the related components. As for the main bridge chip substrate, it is connected with the bonding pad of the motherboard through the solder balls arranged at the bottom solder layer 14, so that the main bridge chip can obtain the related working voltages and proceed the work.
In FIG. 2, it further comprises multiple working connection regions. The CPU working connection region 201 represents the region where the main bridge chip and the CPU are connected together. This region includes the signal bonding pads for connecting to the CPU. The region also includes some ground bonding pads (the black dots) and some CPU power bonding pads (marked with “T”). The CPU power ring 201A, more particularly, represents a region of the power ring on the main bridge chip, wherein the CPU working connection region 201 is connected with the CPU power bonding pads. In addition, the memory working connection region 202 represents the region in which bonding pads are located for connecting the main bridge chip and the memory locates. The bonding pads include the signal bonding pads for connecting the memory (SRAM for example), and also some ground bonding pads as well as some memory power bonding pads (marked with “M”). The memory power ring 202A represents a region of the main bridge chip power ring, which is the region located in the memory working connection region 202 and being connected to the memory power bonding pads. Furthermore, the subalternate bridge working connection region 203 represents the bonding pad region where the main bridge chip and the subalternate bridge are connected. These bonding pads include not only the signal bonding pads connecting to the subalternate bridge chip, but also several ground bonding pads and subalternate bridge power bonding pads (marked as “V”). The subalternate bridge power ring 203A represents a region of the main bridge chip power ring, which is the region connecting the subalternate bridge working connection region 203 to the subalternate bridge power bonding pads. Moreover, the AGP working connection region 204 represents the bonding pad region connecting the main bridge chip and the AGP component. Wherein, the bonding pads include both signal bonding pads connecting the AGP component and the several ground bonding pads as well as some AGP power bonding pads (marked as “A”). The AGP power ring 204A then represents the region of the main bridge chip power ring, which is the region connecting the AGP working connection region 204 and the AGP power bonding pads. It should be noted in FIG. 2 that the ground bonding pads and the signal bonding pads are depicted as black dots 207 and unfilled circles 208 respectively.
Even though the conventional power layer 13 is partitioned in plane according to the layout in FIG. 2, the power layer after partitioning still cannot be fully used. For example, the region 205 represents the actually utilized power path of the CPU working connection region 201. Since the power path 205 is connected at one side of the CPU working connection region 201, the inductance is not uniformly distributed on both sides of the CPU working connection region 201, causing fluctuation of the supplied voltage. In other words, the inductance level is higher for the CPU located further away from the power path 205, and it is lower for the CPU located closer to the power path 205, causing the supplied voltage to be relatively unstable. In addition, from the distribution of power layer 13 shown in FIG. 2, it can be seen that the power rings 201A, 202A, 203A, and 204A all have different widths. For example, the regions indicated in 202B or 202C depict different widths or missing corners, where the inductance levels of these regions are high. Therefore, when operating under high speeds, the power layer 13 often cannot provide current in a timely manner. This results in a rather large ground/bounce effect, further resulting in unstable high-frequency signals, so as to jeopardize the normal data-processing activities of the entire system.